The present invention relates to engine control systems and, more particularly, to a microprocessor-based engine control system having queued control data flow between the CPU and peripheral devices.
Current microprocessor-based engine control systems must communicate with a number of peripheral data devices. In operation, data is sent to various parts of the control system through these peripheral devices. In addition, data is received and processed by the control system through these same devices. Examples of peripheral data devices include: serial peripheral interfaces (SPI), serial communications interfaces (SCI), analog-to-digital converters (A/D), and controller area networks (CAN). To facilitate data transfer among and between these devices, and to minimize overhead on the system CPU, the data is organized into lists or queues.
Present engine control system designs require that each port interface contain its own queue and queue controller. This results in an inflexible system architecture in terms of queue size and port interface design. Thus, it is difficult to modify the queue structure of the overall system in terms of the number of queues per device, size of the queue, and/or the type of queue trigger, for example.
It is an object of the invention to provide an improved queued port data controller for microprocessor-based engine control systems.
The present invention overcomes the drawbacks of these prior engine control systems through the provision of an engine control system comprising a host processor in operative communication with a data bus and a plurality of peripheral devices for communicating engine operating parameters. Each of the peripheral devices include a first and second transaction register for storing communication parameters for each of the corresponding plurality of peripheral devices. The control system also includes a queued port rate register (QRR) including a memory unit in operative communication with the plurality of peripheral devices for storing data for transmission to the plurality of peripheral devices in accordance with the first and second transaction registers. The system further includes a peripheral counter in operative communication with each of the plurality of peripheral devices. The peripheral counter is adapted to interrogate each of the plurality of peripheral devices and, when data has been written to one of the peripheral devices, update the peripheral device according to the memory unit data.
The present invention is advantageous in that it simplifies the design of each port interface and provides improved flexibility in the queue structure of the overall control system.
Another advantage of the present invention is that the size of the integrated circuit area, i.e., the die size, required for the disclosed queue controller is less than the sum of the die size for the individual queue controllers previously employed.
A further advantage is that the disclosed state machine controls the flow of data to and from the RAM and the external devices without the need for CPU intervention.
Other object and advantages of the invention will become apparent upon reading the following detailed description and appended claims, and upon reference to the accompanying drawings.